1. Technical Field
The invention relates to the technical field of semiconductor memories with a dimension below 20 nm, in particular to a tunnel transistor structure integrated with a RRAM and a manufacturing method thereof.
2. Description of Related Art
Information reading and writing of the RRAM is realized by reading or changing the resistance of the resistance-variable material. Usually, the resistance-variable material has a high resistance state and a low resistance state. The RRAM stores information using these kinds of materials by switching between the two states. FIG. 1 illustrates a sectional view of a typical RRAM unit. In this RRAM unit 10, a resistance-variable storage layer 12 is placed between a top electrode 11 and a bottom electrode 13. By the action of an external voltage, the resistance of the resistance-variable storage layer 12 can be in a high state and a low state, which are represented by “0” and “1”. With different voltages, the resistance of the RRAM can be switched between the high state and the low state to realize information storage. The RRAM has advantages of simple preparation, high storage density, low operation voltage, quick speed of reading and writing, long service time, nondestructive access, low power, and in comparison with CMOS (complementary metal-oxide-semiconductor), high process compatibility, and therefore is regarded as one of the most powerful candidates for the next generation of “universal” memories.
At present, MOS transistor structures (metal-oxide-semiconductors, namely field effect transistors) are usually adopted as the driving circuit of the RRAM, and the RRAM is usually formed in the subsequent interconnection procedure of the MOS transistor. Meanwhile, along with the continuous development of the technologies of integrated circuit devices, the leakage current between the drain region and drain region rises rapidly along with the reduction of the length of the trench. Below 30 nm, it is necessary to use a new device to realize a small leakage current so as to lower the power consumption of the chip. One of the schemes to solve the above mentioned problem is to adopt a tunnel transistor structure. The tunnel transistor has a very tiny leakage current and can further reduce the dimensions of the circuit and the voltage to lower the power consumption of the chip.